FIG. 14 shows a simplified exemplary configuration of a conventional radio circuit apparatus. Only the desired reception band of a signal received by an antenna 1 is input to a low noise amplifier 3 via an antenna sharing device 2. The signal amplified by the low noise amplifier 3 is input to an orthogonal demodulator 4. The orthogonal demodulator 4 orthogonally demodulates the amplified signal using a local signal (frequency f2) supplied from a reception PLL circuit 100b and a signal obtained by phase shifting the local signal with a 90° phase shifter 5, and obtains a baseband signal I/Q from which the carrier component has been eliminated.
The reception PLL circuit 100b is composed of a voltage-controlled oscillator 101, a low-pass filter 102, a phase detector 103 and a frequency divider 104b, and outputs the signal of frequency f2 obtained by multiplying the frequency of the output signal of a TCXO (temperature controlled crystal oscillator) 105 by a frequency division ratio B of the frequency divider 104b. 
An orthogonal modulator 106 on the transmission side uses the baseband signal I/Q to modulate a carrier signal composed of a local signal (frequency f1) supplied from a transmission PLL circuit 100a and a signal obtained by phase shifting the local signal with a 90° phase shifter 107, and outputs the result. The output of the orthogonal modulator 106 is amplified by a power amplifier 10 and supplied to the antenna sharing device 2. Only the desired transmission band is transmitted to the antenna 1 by the antenna sharing device 2.
The transmission PLL circuit 100a, similarly to the reception PLL circuit 100b, is composed of a voltage-controlled oscillator 101, a low-pass filter 102, a phase detector 103 and a frequency divider 104a, and outputs a signal of frequency f1 obtained by multiplying the frequency of the output signal of the TCXO 105 by a frequency division ratio A of the frequency divider 104a. 
Note that in both the transmission PLL circuit 100a and the reception PLL circuit 100b, the frequency division ratios A and B are set in accordance with the channel of the desired frequency.
Incidentally, a configuration using a delta-sigma modulator (Δ-Σ modulator; also referred to as a sigma-delta modulator (Σ-Δ modulator)) in order to precisely obtain the output frequency of a frequency synthesizer that uses PLL circuits at small frequency intervals is disclosed in patent document 1, for example. This is a method that realizes a dividing ratio with decimal point accuracy as average data by periodically changing the dividing ratio. The delta-sigma modulator is used in order to periodically change the dividing ratio.
Patent document 1 further discloses a configuration that is able to add the modulation component to data for fractional control supplied to the delta-sigma modulator (see patent document 1, FIG. 17). A configuration thereby is obtained in which a frequency synthesizer using PLL circuits combines the function of an orthogonal modulator that performs modulation using a baseband signal I/Q with the generation of local signals.    Patent Document 1: JP 2001-237709A    Non-patent Document 1: “A 17-bit Oversampling D-to-A Conversion Technology using Multistage Noise Shaping,” IEEE Journal of Solid-State Circuits, Vol. 24, No. 4, August 1989, p. 971, FIG. 4